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CY7C372I
UltraLogicTM 64-Macrocell Flash CPLD
Features
* 64 macrocells in four logic blocks * 32 I/O pins * Five dedicated inputs including two clock pins * In-System Reprogrammable (ISRTM) Flash technology -- JTAG interface * Bus Hold capabilities on all I/Os and dedicated inputs * No hidden delays * High speed -- fMAX = 125 MHz -- tPD = 10 ns -- tS = 5.5 ns -- tCO = 6.5 ns * Fully PCI compliant * 3.3V or 5.0V I/O operation * Available in 44-pin PLCC, TQFP, and CLCC packages * Pin-compatible with the CY7C371i
Functional Description
The CY7C372I is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370iTM family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C372I is designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. Like all of the UltraLogicTM FLASH370i devices, the CY7C372I is electrically erasable and ISR, which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. The 64 macrocells in the CY7C372I are divided between four logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource--the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect.
Logic Block Diagram
INPUTS
CLOCK INPUTS 2 INPUT/CLOCK MACROCELLS 2 LOGIC BLOCK D 8 I/Os I/O24-I/O31
3 INPUT MACROCELLS 2 8 I/Os I/O0-I/O7 LOGIC BLOCK A
36 16
PIM
36 16
8 I/Os I/O8-I/O15
LOGIC BLOCK B
36 16
36 16
LOGIC BLOCK C
8 I/Os I/O16-I/O23
16
16
Cypress Semiconductor Corporation Document #: 38-03033 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 16, 2004
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Selection Guide
7C372i-125 Maximum Propagation Delay[1] , tPD (ns) 10 5.5 6.5 75 Minimum Set-up, tS (ns) Maximum Clock to Output[1], tCO (ns) Typical Supply Current, ICC (mA) 7C372i-100 12 6.0 6.5 75 7C372i-83 15 8 8 75 7C372iL-83 15 8 8 45
CY7C372I
7C372i-66 20 10 10 75
7C372iL-66 20 10 10 45
Pin Configurations
PLCC TopView
I/O 1 I/O 0 GND VCCIO I/O31 I/O30 I/O29 I/O28 I/O 4 I/O 3 I/O 2
CLCC TopView
I/O31 I/O30 I/O29 I/O28 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 GND VCC I/O5/SCLK I/O6 I/O7 I0 ISREN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11
6 5 4 3 2 1 44 43 42 41 40 I/O5/SCLK I/O6 I/O7 I0 ISREN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O13 /SMODE I/O14 I/O15 V CCINT GND I/O16 I/O17 I/O18 I/O19 /SDO I/O20 I/O27/SDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 I2 I/O23 I/O22 I/O21
6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O 13 /SMODE I/O14 I/O15 V CC GND I/O16 I/O17 I/O18 I/O19 /SDO I/O20 I/O27/SDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 I2 I/O23 I/O22 I/O21
Note: 1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
Document #: 38-03033 Rev. *A
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Functional Description
Like all members of the FLASH370i family, the CY7C372I is rich in I/O resources. Every two macrocells in the device feature an associated I/O pin, resulting in 32 I/O pins on the CY7C372I. In addition, there are three dedicated inputs and two input/clock pins. Finally, the CY7C372I features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used. or the type of application, the timing parameters on the CY7C372I remain the same. Logic Block The number of logic blocks distinguishes the members of the FLASH370i family. The CY7C372I includes four logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Product Term Array The product term array in the FLASH370i logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex functions to be implemented in a single pass through the device. Product Term Allocator The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370 PLDs. Note that product term allocation is handled by software and is invisible to the user. I/O Macrocell Half of the macrocells on the CY7C372I have separate I/O pins associated with them. In other words, each I/O pin is shared by two macrocells. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed. It also has polarity control, and two global clocks to trigger the register. The I/O macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. Buried Macrocell The buried macrocell is very similar to the I/O macrocell. Again, it includes a register that can be configured as combinatorial, as a D flip-flop, a T flip-flop, or a latch. The clock for this register has the same options as described for the I/O macrocell. One difference on the buried macrocell is the addition of input register capability. The user can program the buried macrocell to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neigh-
CY7C372I
boring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C372I to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Programming For an overview of ISR programming, refer to the FLASH370i Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of ISR capabilities, refer to the Cypress application note, "An Introduction to In System Reprogramming with FLASH370i." PCI Compliance The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The simple and predictable timing model of FLASH370i ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. 3.3V or 5.0V I/O operation The FLASH370i family can be configured to operate in both 3.3V and 5.0V systems. All devices have two sets of VCC pins: one set, VCCINT, for internal operation and input buffers, and another set, VCCIO, for I/O output drivers. VCCINT pins must always be connected to a 5.0V power supply. However, the VCCIO pins may be connected to either a 3.3V or 5.0V power supply, depending on the output requirements. When VCCIO pins are connected to a 5.0V source, the I/O voltage levels are compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ranges. Bus Hold Capabilities on all I/Os and Dedicated Inputs In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. Design Tools Development software for the CY7C372I is available from Cypress's WarpTM, Warp ProfessionalTM, and Warp EnterpriseTM software packages. Please refer to the data sheets on these products for more details. Cypress also actively supports almost all third-party design tools. Please refer to third-party tool support for further information. Page 3 of 13
Document #: 38-03033 Rev. *A
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V DC Program Voltage .....................................................12.5V
CY7C372I
Output Current into Outputs ........................................ 16 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Commercial Industrial Military[2] Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC VCCINT VCCIO
5V 0.25V 5V 0.25V or 3.3V 0.3V 5V 0.5V 5V 0.5V 5V 0.5V 3.3V 0.3V
Electrical Characteristics Over the Operating Range[3, 4]
Parameter VOH VOHZ VOL VIH VIL IIX IOZ Description Output HIGH Voltage Output HIGH Voltage with Output Disabled[8] Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Test Conditions VCC = Min. IOH = -3.2 mA (Com'l/Ind)[5] IOH = -2.0 mA (Mil) VCC = Max. IOH = 0 A (Com'l/Ind)[5, 6] IOH = -50 A (Com'l/Ind)[5, 6] VCC = Min. IOL = 16 mA (Com'l/Ind)[5] IOL = 12 mA (Mil) Guaranteed Input Logical HIGH Voltage for all Inputs[7] Guaranteed Input Logical LOW Voltage for all Inputs[7] VI = Internal GND, VI = VCC VCC = Max., VO = GND or VO = VCC, Output Disabled VCC = Max., VO = 3.3V, Output Disabled[6] IOS ICC Output Short Circuit Current[8, 9] Power Supply Current [10] VCC = Max., VOUT = 0.5V VCC = Max., IOUT = 0 mA, f = 1 MHz, VIN = GND, VCC VCC = Min., VIL = 0.8V VCC = Min., VIH = 2.0V VCC = Max. VCC = Max. Com'l/Ind. Com'l "L" -66 Military IBHL IBHH IBHLO IBHHO Input Bus Hold LOW Sustaining Current Input Bus Hold HIGH Sustaining Current Input Bus Hold LOW Overdrive Current Input Bus Hold HIGH Overdrive Current +75 -75 +500 -500 2.0 -0.5 -10 -50 0 -30 75 45 75 -70 Min. 2.4 2.4 4.0 3.6 0.5 0.5 7.0 0.8 +10 +50 -125 -160 125 75 200 Typ. Max. Unit V V V V V V V V A A A mA mA mA mA A A A A
Notes: 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC = VCCINT. 5. For SDO: IOH =-2 mA, IOL = 2 mA. 6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note "Understanding Bus Hold" for additional information. 7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 9. Tested initially and after any design or process changes that may affect these parameters. 10. Measured with 16-bit counter programmed into each logic block.
Document #: 38-03033 Rev. *A
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Capacitance[9]
Parameter CI/O
[11, 12]
CY7C372I
Description Input Capacitance Clock Signal Capacitance
Test Conditions VIN = 5.0V at f = 1 MHz VIN = 5.0V at f = 1 MHz
Min. 5
Max. 8 12
Unit pF pF
CCLK
Inductance[9]
Parameter L Description Maximum Pin Inductance Test Conditions VIN = 5.0V at f = 1 MHz 44-Lead CLCC 2 44-Lead PLCC 5 Unit nH
Endurance Characteristics[9]
Parameter N Description Maximum Reprogramming Cycles Test Conditions Normal Programming Conditions Max. 100 Unit Cycles
AC Test Loads and Waveforms
238 (com'l) 319 (mil) 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE 170 (com'l) 236 (mil) 238 (com'l) 319 (mil) 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 3.0V 90% GND < 2 ns 10% 90% 10% 170 (com'l) 236 (mil)
(a)
(b)
ALL INPUT PULSES
Equivalent to:
THEVENIN EQUIVALENT 99 (com'l) 136 (mil) 2.08V(com'l) OUTPUT 2.13V(mil)
(c)
< 2 ns
Parameter[13] tER(-)
Vx 1.5V V OH
Output Waveform Measurement Level
0.5V
VX
tER(+)
2.6V V OL 0.5V VX
tEA(+)
1.5V 0.5V VX V OH
tEA(-)
Vthe VX 0.5V V OL
(d) Test Waveforms
Note: 11. CI/O for dedicated Inputs, and for I/O pins with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max. 12. CI/O for CLCC package is 15 pF Max. 13. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Document #: 38-03033 Rev. *A
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Switching Characteristics Over the Operating Range [14]
7C372i-125 Parameter tPD tPDL tPDLL tEA tER tWL tWH tIS tIH tICO tICOL Description Input to Combinatorial Output[1] Input to Output Through Transparent Input or Output Latch[1] Input to Output Through Transparent Input and Output Latches[1] Input to Output Enable[1] Input to Output Disable Clock or Latch Enable Input LOW Time[9] Clock or Latch Enable Input HIGH Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combinatorial Output[1] Input Register Clock or Latch Enable to Output Through Transparent Output Latch[1] Clock or Latch Enable to Output[1] Set-Up Time from Input to Clock or Latch Enable Register or Latch Data Hold Time Output Clock or Latch Enable to Output Delay (Through Memory Array)[1] Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable Maximum Frequency with Internal Feedback in Output Registered Mode (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[9] Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO)[9] Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH))[9] Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[9, 15] Input Register Clock to Output Register Clock Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS)[9] 8 10 0 125 5.5 0 14 10 12 0 100 Time[9] Input Register or Latch Set-Up Time 3 3 2 2 14 16 Min. Max. 10 13 15 14 14 3 3 2 2 16 18 Combinatorial Mode Parameters 12 15 16 16 16 4 4 3 3 19 21 15 18 19 19 19 7C372i-100 Min. Max. 7C372i-83 7C372iL-83 Min. Max.
CY7C372I
7C372i-66 7C372iL-66 Min. Max. 20 22 24 24 24 5 5 4 4 24 26 Unit ns ns ns ns ns ns ns ns ns ns ns
Input Registered/Latched Mode Parameters
Output Registered/Latched Mode Parameters tCO tS tH tCO2 tSCS tSL tHL fMAX1 6.5 6 0 16 12 15 0 83 6.5 8 0 19 15 20 0 66 8 10 0 24 10 ns ns ns ns ns ns ns MHz
fMAX2
153.8
153.8
125
100
MHz
fMAX3 tOH-tIH 37x tICS fMAX4
83.3 0
80 0
62.5 0
50 0
MHz ns
Pipelined Mode Parameters 8 125 10 100 12 83.3 15 66.6 ns MHz
Notes: 14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C372I. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03033 Rev. *A
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Switching Characteristics Over the Operating Range (continued)[14]
7C372i-125 Parameter Reset/Preset Parameters tRW tRR tRO tPW tPR tPO fTAP t3.3IO Asynchronous Reset Width[9] Asynchronous Reset Recovery Time[9] Asynchronous Reset to Output Asynchronous Preset Width[9] Asynchronous Preset Recovery Time[9] Asynchronous Preset to Output[1] Tap Controller Frequency 3.3V I/O Mode Timing Adder 500 1
[1]
CY7C372I
7C372i-83 7C372iL-83 Min. 15 17 18 21 15 17 18 21 500 1 1 500 1 20 22 26 Max. 7C372i-66 7C372iL-66 Min. 20 22 26 Max. Unit ns ns ns ns ns ns kHz ns
7C372i-100 Min. 12 14 Max.
Description
Min. 10 12
Max.
16 10 12 16 500 12 14
Tap Controller Parameter 3.3V I/O Mode Parameters
Switching Waveforms
Combinatorial Output
INPUT tPD COMBINATORIAL OUTPUT
Registered Output
INPUT tS CLOCK tCO REGISTERED OUTPUT tH
tWH CLOCK
tWL
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Switching Waveforms (continued)
Latched Output
INPUT tS LATCH ENABLE tPDL LATCHED OUTPUT tCO tH
CY7C372I
Registered Input
REGISTERED INPUT tIS INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tIH
tWH CLOCK
tWL
Clock to Clock
REGISTERED INPUT
INPUT REGISTER CLOCK tICS OUTPUT REGISTER CLOCK tSCS
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Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT
CY7C372I
tPDLL LATCHED OUTPUT tICOL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tSL tHL
tWH LATCH ENABLE
tWL
Asynchronous Reset
tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK
Asynchronous Preset
tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK
Document #: 38-03033 Rev. *A
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Switching Waveforms (continued)
Output Enable/Disable
INPUT tER OUTPUTS tEA
CY7C372I
Ordering Information
Speed (MHz) 125 100 83 Ordering Code CY7C372I-125JC CY7C372I-100JC CY7C372I-100JI CY7C372I-83JC CY7C372I-83JI CY7C372I-83YMB 83 66 CY7C372IL-83JC CY7C372I-66JC CY7C372I-66JI CY7C372I-66YMB 66 CY7C372IL-66JC Package Name J67 J67 J67 J67 J67 Y67 J67 J67 J67 Y67 J67 Package Type 44-Lead Plastic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Ceramic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Ceramic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier Operating Range Commercial Commercial Industrial Commercial Industrial Military Commercial Commercial Industrial Military Commercial
Document #: 38-03033 Rev. *A
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MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Subgroups
CY7C372I
Switching Characteristics
Parameter tPD tCO tICO tS tH tIS tIH tICS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Subgroups
Package Diagrams
44-Lead Plastic Leaded Chip Carrier J67
51-85003-*A
Document #: 38-03033 Rev. *A
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Package Diagrams (continued)
44-Pin Ceramic Leaded Chip Carrier Y67
CY7C372I
51-80014-**
ISR, UltraLogic, FLASH370, FLASH370i, Warp, Warp Professional, and Warp Enterprise, are trademarks of Cypress Semiconductor Corporation.
Document #: 38-03033 Rev. *A
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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Document History Page
Document Title: CY7C372I UltraLogicTM 64-Macrocell Flash CPLD Document Number: 38-03033 REV. ** *A ECN NO. Issue Date 106378 213375 06/18/01 See ECN Orig. of Change SZV FSG Decsription of Change Change from Spec# 38-00498 to 38-03033
CY7C372I
Added note to title page: "Use Ultra37000 For All New Designs"
Document #: 38-03033 Rev. *A
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